1. Field of the Invention
The present invention generally relates to integrated circuits, and, more particularly to a clock and data recovery circuit.
2. Description of the Related Art
A clock and data recovery (CDR) circuit is commonly used in a high speed data communication system. Generally, the high speed data communication system receives an input signal without an accompanying clock signal. An absence of the accompanying clock signal may result in undersampling or oversampling of the input signal. Thus, a CDR circuit is used in the high speed data communication system to generate a clock signal at a frequency that is equal to the frequency of the input signal. Further, the clock signal samples the input signal at the frequency of the clock signal.
Typically, a conventional CDR circuit includes a phase-frequency detector (PFD) circuit, a digital-to-analog converter (DAC), an oscillator, and a data sampler. The PFD circuit determines a frequency difference between a frequency of a reference clock signal and a frequency of the clock signal, and generates a digital control signal (also referred to as a “frequency lock mode”). The frequency of the reference clock signal is equal to the frequency of the input signal or multiples of the frequencies of the input signal.
The DAC includes multiple current sources and switches. The DAC is connected to the PFD circuit to receive the digital control signal. The digital control signal selects the multiple current sources by controlling their corresponding switches. Thus, the DAC outputs an output current based on the digital control signal. The oscillator is connected to the DAC to receive the output current and generate the clock signal. As the oscillator generates the clock signal based on the reference clock signal, the frequency of the clock signal is equal to the frequency thereof. Thus, the frequency of the clock signal is locked at the frequency of the reference clock signal (i.e., the frequency of the input signal).
After locking the frequency of the clock signal, the PFD circuit detects a phase difference between a phase of the input signal and a phase of the clock signal (also referred to as a “phase lock mode”). The digital control signal varies based on the detected phase difference, and in turn modulates the phase of the clock signal. Thus, the phase of the clock signal is locked at the phase of the input signal. The data sampler is connected to the oscillator to receive the clock signal, and samples the input signal at the frequency of the clock signal.
The frequency of the clock signal depends on the output current which in turn depends on a step size of the DAC. The step size of the DAC indicates a fractional change of the frequency of the clock signal corresponding to a bit change of the digital control signal (also known as “parts per million frequency step size” or “ppm frequency step size”). Further, the ppm frequency step size depends on the bias current and the frequency of the clock signal. For a constant output current, the frequency of the clock signal may vary with variation in temperature. Further, the bias current varies significantly with process-voltage-temperature (PVT) variations. Thus, the ppm frequency step size varies significantly with the PVT variations. Moreover, a variation in the ppm frequency step size results in the variation of the range of the output current that the DAC can provide to the oscillator. Thus, for generating the clock signal with the frequency and phase equal to the frequency and phase of the input signal, the variation in the ppm frequency step size is undesirable. Such a DAC, when used in the CDR circuit, may provide inaccurate frequency of the clock signal, leading to undersampling or oversampling of the input signal.
A known technique to overcome the aforementioned problem is to increase or decrease the step size of the DAC. However, a DAC with a small step size includes a large number of current sources and switches to adjust the output current accurately based on the digital control signal. Thus, a decrease in the step size increases the size and complexity of the DAC. A DAC with a large step size includes a small number of current sources and switches.
However, such a DAC provides a large change in frequency with one bit change in the digital control signal. Further, the current requirement by the current sources in such DAC increases with increase in the step size of the DAC, thereby leading to poor power supply rejection. Thus, a DAC with an optimum step size and constant ppm frequency step size is required for the CDR circuit to generate the clock signal at a frequency equal to the frequency of the reference clock signal or a multiple of the frequency of the reference clock signal.
Therefore, it would be advantageous to have a CDR circuit that generates the clock signal that is independent of bias current and PVT variations, maintains a constant ppm frequency step size, and that overcomes the above-mentioned limitations of the conventional CDR circuit.